https://github.com/chipsalliance/UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
https://github.com/chipsalliance/UHDM

ieee-standard listener serialization systemverilog vpi-api vpi-interface

Last synced: about 1 month ago
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Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

• Host: GitHub
• URL: https://github.com/chipsalliance/UHDM
• Owner: chipsalliance
• License: apache-2.0
• Created: 2019-12-13T04:25:50.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2024-10-07T01:35:02.000Z (3 months ago)
• Last Synced: 2024-11-05T21:48:52.371Z (about 2 months ago)
• Topics: ieee-standard, listener, serialization, systemverilog, vpi-api, vpi-interface
• Language: C++
• Homepage:
• Size: 4.39 MB
• Stars: 198
• Watchers: 20
• Forks: 40
• Open Issues: 15
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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