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https://github.com/chipsalliance/firrtl

Flexible Intermediate Representation for RTL
https://github.com/chipsalliance/firrtl

compiler firrtl hardware intermediate representation transformation

Last synced: 10 days ago
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Flexible Intermediate Representation for RTL

Host: GitHub
URL: https://github.com/chipsalliance/firrtl
Owner: chipsalliance
License: apache-2.0
Created: 2015-02-13T23:04:44.000Z (over 9 years ago)
Default Branch: 1.6.x
Last Pushed: 2024-03-20T16:12:09.000Z (8 months ago)
Last Synced: 2024-04-13T21:02:49.940Z (7 months ago)
Topics: compiler, firrtl, hardware, intermediate, representation, transformation
Language: Scala
Homepage: https://www.chisel-lang.org/firrtl/
Size: 56.1 MB
Stars: 690
Watchers: 63
Forks: 174
Open Issues: 286
Metadata Files:
- Readme: README.md
- License: LICENSE.apache
- Codeowners: .github/CODEOWNERS