https://github.com/chipsalliance/firrtl

Flexible Intermediate Representation for RTL
https://github.com/chipsalliance/firrtl

compiler firrtl hardware intermediate representation transformation

Last synced: about 1 month ago
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Flexible Intermediate Representation for RTL

• Host: GitHub
• URL: https://github.com/chipsalliance/firrtl
• Owner: chipsalliance
• License: apache-2.0
• Archived: true
• Created: 2015-02-13T23:04:44.000Z (about 10 years ago)
• Default Branch: 1.6.x
• Last Pushed: 2024-08-20T18:13:34.000Z (8 months ago)
• Last Synced: 2024-11-01T02:35:45.263Z (6 months ago)
• Topics: compiler, firrtl, hardware, intermediate, representation, transformation
• Language: Scala
• Homepage: https://www.chisel-lang.org/firrtl/
• Size: 56 MB
• Stars: 726
• Watchers: 61
• Forks: 177
• Open Issues: 287
• Metadata Files:
  • Readme: README.md
  • License: LICENSE.apache
  • Codeowners: .github/CODEOWNERS

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