https://github.com/chipsalliance/fpga-interchange-tests
Repository to run extensive tests on the FPGA interchange format
https://github.com/chipsalliance/fpga-interchange-tests
f4pga
Last synced: 6 months ago
JSON representation
Repository to run extensive tests on the FPGA interchange format
- Host: GitHub
- URL: https://github.com/chipsalliance/fpga-interchange-tests
- Owner: chipsalliance
- License: isc
- Created: 2021-04-15T08:01:28.000Z (over 4 years ago)
- Default Branch: main
- Last Pushed: 2023-04-02T03:06:14.000Z (over 2 years ago)
- Last Synced: 2025-04-10T00:38:52.517Z (6 months ago)
- Topics: f4pga
- Language: Verilog
- Homepage: https://chipsalliance.github.io/fpga-interchange-tests
- Size: 3.59 MB
- Stars: 8
- Watchers: 8
- Forks: 9
- Open Issues: 28
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# FPGA interchange tests
This repository contains end-to-end tests to verify the correctness of the whole FPGA interchange flow.
## Steps to run
To prepare the environment run:
```
make env
```
Enter the environment by running:
```
source env/conda/bin/activate fpga-interchange
```
To update the RapidWright data run:
```
make update
```
To build the CMake infrastructure and the required tools run:
```
make build
```
A set of targets are generated to run every step of the flow:
```
cd build
# Run all place and route tests until bitstream generation
make all-tests
# Run all validation tests through fasm2bels
make all-validation-tests
# Run all vendor bitstream generation tests
make all-vendor-bit-tests
# Run all simulation tests; pre- and post-synthesis and, if enabled, post-fasm2bels
make all-simulation-tests
```