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https://github.com/chipsalliance/rocket-chip-blocks
RTL blocks compatible with the Rocket Chip Generator
https://github.com/chipsalliance/rocket-chip-blocks
Last synced: 4 days ago
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RTL blocks compatible with the Rocket Chip Generator
- Host: GitHub
- URL: https://github.com/chipsalliance/rocket-chip-blocks
- Owner: chipsalliance
- License: apache-2.0
- Created: 2022-06-01T16:59:12.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2024-06-26T18:59:08.000Z (5 months ago)
- Last Synced: 2024-11-01T02:35:45.635Z (9 days ago)
- Language: Scala
- Size: 655 KB
- Stars: 14
- Watchers: 16
- Forks: 15
- Open Issues: 5
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Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# RTL Blocks for the Rocket Chip Generator
This repository contains RTL generators for a variety of IO peripheral blocks that are designed to be compatible with the Rocket Chip SoC Generator
This repository is a fork of https://github.com/sifive/sifive-blocks, which it replaces.