https://github.com/chipsalliance/rocket-chip-inclusive-cache

An RTL generator for a last-level shared inclusive TileLink cache controller
https://github.com/chipsalliance/rocket-chip-inclusive-cache

Last synced: 3 months ago
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An RTL generator for a last-level shared inclusive TileLink cache controller

• Host: GitHub
• URL: https://github.com/chipsalliance/rocket-chip-inclusive-cache
• Owner: chipsalliance
• License: apache-2.0
• Created: 2022-06-01T18:25:06.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2024-08-15T21:36:08.000Z (6 months ago)
• Last Synced: 2024-11-01T02:35:45.628Z (3 months ago)
• Language: Scala
• Size: 173 KB
• Stars: 15
• Watchers: 15
• Forks: 19
• Open Issues: 11
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# Rocket Chip SoC Inclusive Cache Generator

This `block` package contains an RTL generator for creating instances of a coherent, last-level, inclusive cache.

The `InclusiveCache` controller enforces coherence among a set of caching clients

using an invalidation-based coherence policy implemetated on top of the the TileLink 1.8.1 coherence messaging protocol.

This policy is implemented using a full-map of directory bits stored with each cache block's metadata tag.

The `InclusiveCache` is a TileLink adapter;

it can be used as a drop-in replacement for Rocket-Chip's `tilelink.BroadcastHub` coherence manager.

It additionally supplies a SW-controlled interface for flusing cache blocks based on physical addresses.

The following parameters of the cache are easily `Config`-urable: 

size, ways, banking and sub-banking factors, external bandwidth, network interface buffering.

Stand-alone unit tests coming soon.

This repository is a replacement for https://github.com/sifive/block-inclusivecache-sifive