https://github.com/chipsalliance/yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
https://github.com/chipsalliance/yosys-f4pga-plugins
eda f4pga fpga toolchain xilinx xilinx-fpga yosys yosys-plugin
Last synced: 6 months ago
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Plugins for Yosys developed as part of the F4PGA project.
- Host: GitHub
- URL: https://github.com/chipsalliance/yosys-f4pga-plugins
- Owner: chipsalliance
- License: apache-2.0
- Created: 2019-11-07T12:13:37.000Z (almost 6 years ago)
- Default Branch: main
- Last Pushed: 2024-05-14T20:35:44.000Z (over 1 year ago)
- Last Synced: 2025-04-10T00:38:58.054Z (6 months ago)
- Topics: eda, f4pga, fpga, toolchain, xilinx, xilinx-fpga, yosys, yosys-plugin
- Language: Verilog
- Homepage: https://f4pga.org
- Size: 4.57 MB
- Stars: 83
- Watchers: 17
- Forks: 47
- Open Issues: 83
-
Metadata Files:
- Readme: README.md
- Contributing: CONTRIBUTING.md
- License: LICENSE
- Code of conduct: CODE_OF_CONDUCT.md
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README
# Yosys F4PGA Plugins
This repository contains plugins for [Yosys](https://github.com/YosysHQ/yosys.git) developed as [part of the F4PGA project](https://f4pga.org).
## Design introspection plugin
Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a
selection of objects.
Additionally provides functions to convert selection on TCL lists.
Following commands are added with the plugin:
* get_cells
* get_nets
* get_pins
* get_ports
* get_count
* selection_to_tcl_list
## FASM plugin
Writes out the design's [fasm features](https://fasm.readthedocs.io/en/latest/) based on the parameter annotations on a
design cell.
The plugin adds the following command:
* write_fasm
## Integrate inverters plugin
Implements a pass that integrates inverters into cells that have ports with the 'invertible_pin' attribute set.
The plugin adds the following command:
* integrateinv
## Parameters plugin
Reads the specified parameter on a selected object.
The plugin adds the following command:
* getparam
## QuickLogic IOB plugin
[QuickLogic IOB plugin](./ql-iob-plugin/) annotates IO buffer cells with information from IO placement constraints.
Used during synthesis for QuickLogic EOS-S3 architecture.
The plugin adds the following command:
* quicklogic_iob
## QuickLogic QLF FPGAs plugin
[QuickLogic QLF plugin](./ql-qlf-plugin) extends Yosys with synthesis support for `qlf_k4n8` and `qlf_k6n10` architectures.
The plugin adds the following command:
* synth_quicklogic
* ql_dsp
Detailed help on the supported command(s) can be obtained by running `help ` in Yosys.
## SDC plugin
Reads Standard Delay Format (SDC) constraints, propagates these constraints across the design and writes out the
complete SDC information.
The plugin adds the following commands:
* read_sdc
* write_sdc
* create_clock
* get_clocks
* propagate_clocks
* set_false_path
* set_max_delay
* set_clock_groups
## XDC plugin
Reads Xilinx Design Constraints (XDC) files and annotates the specified cells parameters with properties such as:
* INTERNAL_VREF
* IOSTANDARD
* SLEW
* DRIVE
* IN_TERM
* LOC
* PACKAGE_PIN
The plugin adds the following commands:
* read_xdc
* get_iobanks
* set_property
* get_bank_tiles
## SystemVerilog plugin
The SystemVerilog plugin has been moved to [chipsalliance/synlig](https://github.com/chipsalliance/synlig).
## Clock Gating plugin
Performs dynamic power optimization by automatically clock gating registers in design.
For Full documentation check [Lighter](https://github.com/Cloud-V/Lighter).
The plugin adds the following command:
* reg_clock_gating
Detailed help on the supported command(s) can be obtained by running `help ` in Yosys.