https://github.com/choaib-elmadi/getting-started-with-verilog

Getting started with Verilog: Hardware Description Language for digital design.
https://github.com/choaib-elmadi/getting-started-with-verilog

circuit circuit-designing design digital hardware hardware-description-language hdl ics intel verilog verilog-hdl

Last synced: 5 months ago
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Getting started with Verilog: Hardware Description Language for digital design.

• Host: GitHub
• URL: https://github.com/choaib-elmadi/getting-started-with-verilog
• Owner: Choaib-ELMADI
• Created: 2025-02-16T17:00:23.000Z (over 1 year ago)
• Default Branch: master
• Last Pushed: 2025-02-28T19:36:19.000Z (over 1 year ago)
• Last Synced: 2025-07-28T06:32:10.008Z (12 months ago)
• Topics: circuit, circuit-designing, design, digital, hardware, hardware-description-language, hdl, ics, intel, verilog, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 9.87 MB
• Stars: 7
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
[![Choaib ELMADI - Verilog](https://img.shields.io/badge/Choaib_ELMADI-Verilog-8800dd)](https://elmadichoaib.vercel.app) ![Status - Learning](https://img.shields.io/badge/Status-Learning-2bd729) [![Credit - Intel Learning](https://img.shields.io/badge/Credit-Intel_Learning-3b8af2)](https://learning.intel.com/developer/learn/courses/235/verilog-hdl-basics/lessons/37535:2308/verilog-hdl-basics)

# Getting Started with Verilog

Verilog is a hardware description language (HDL) used to model and design digital circuits. It allows engineers to describe the structure and behavior of electronic systems, making it a crucial tool in FPGA and ASIC development.



![What is Verilog](./Images/what-is-verilog.png)



## Verilog Workflow

The process of running Verilog code involves several steps:

1. **Synthesis**: After engineers write the code using Verilog, it is processed by a tool, `similar to a compiler`, to generate a synthesized circuit netlist. Netlists define components and their interconnections, translating Verilog code into a digital logic representation.

2. **Place and Route**: The netlist is mapped to the physical resources of the target architecture, determining the placement of components and routing the connections between them.



![Verilog Processing](./Images/verilog-workflow.png)



## Used Tools

To run and simulate Verilog code, you will need the following tools. Below are links to install them:

- **ModelSim**: A logic simulation tool - [Download link](https://www.intel.com/content/www/us/en/software-kit/660907/intel-quartus-prime-lite-edition-design-software-version-20-1-1-for-windows.html):

  - Select: **Individual Files**

  - Under **Intel® Quartus® Software**, download: **ModelSim-Intel® FPGA Edition (includes Starter Edition)**

- **Quartus Prime Lite**: An FPGA synthesis / implementation tool - [Download link](https://www.intel.com/content/www/us/en/software-kit/825278/intel-quartus-prime-lite-edition-design-software-version-23-1-1-for-windows.html):

  - Select: **Individual Files**

  - Under **Intel® Quartus® Software**, download: **Quartus® Prime (includes Nios II EDS)**

- **MAX10 Device Files**: MAX10 FPGA device information - [Download link](https://www.intel.com/content/www/us/en/software-kit/825278/intel-quartus-prime-lite-edition-design-software-version-23-1-1-for-windows.html):

  - Select: **Individual Files**

  - Under **Devices**, download: **MAX® 10 FPGA device support**

Place all the downloaded files in the same directory, then launch `Quartus Prime Lite` and `ModelSim` to begin your workflow.

## How to Use Simulation Tools

Once you have installed **ModelSim** and **Quartus Prime Lite**, you can follow the guides below to learn how to set up and run simulations:

- **Using ModelSim**: [Step-by-step guide](./Projects/ModelSim/README.md)

- **Using Quartus Prime Lite**: [Step-by-step guide](./Projects/Quartus/README.md)

These guides cover how to:

- Set up a Verilog project

- Write and compile testbenches

- Run simulations and analyze waveforms