https://github.com/choaib-elmadi/risc-v-on-de1-soc-fpga

A simplified RISC-V processor implemented in Verilog and deployed on the DE-1 SoC FPGA board.
https://github.com/choaib-elmadi/risc-v-on-de1-soc-fpga

de1-soc fpga fpga-board fpga-programming fpga-soc hdl implementation processor programming risc risc-v riscv verilog

Last synced: 6 months ago
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A simplified RISC-V processor implemented in Verilog and deployed on the DE-1 SoC FPGA board.

• Host: GitHub
• URL: https://github.com/choaib-elmadi/risc-v-on-de1-soc-fpga
• Owner: Choaib-ELMADI
• Created: 2025-04-05T14:53:33.000Z (6 months ago)
• Default Branch: master
• Last Pushed: 2025-04-14T14:22:19.000Z (6 months ago)
• Last Synced: 2025-04-14T23:46:30.810Z (6 months ago)
• Topics: de1-soc, fpga, fpga-board, fpga-programming, fpga-soc, hdl, implementation, processor, programming, risc, risc-v, riscv, verilog
• Language: Verilog
• Homepage:
• Size: 24.3 MB
• Stars: 4
• Watchers: 1
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
[![Choaib ELMADI - RISC-V](https://img.shields.io/badge/Choaib_ELMADI-RISC--V-8800dd)](https://elmadichoaib.vercel.app) ![Status - Building](https://img.shields.io/badge/Status-Building-2bd729) ![Platform - DE1-SoC](https://img.shields.io/badge/Platform-DE--1_SoC-f7d620)

# RISC-V Processor on DE-1 SoC FPGA

Welcome to the `risc-v-on-de1-soc-fpga` repository! This project implements a simplified RISC-V processor architecture using Verilog and is deployed on the DE-1 SoC FPGA development board.

## Repository Structure

The repository is structured as follows:

- **Single Cycle Processor**: Contains the implementation of the single-cycle RISC-V CPU and its modules.



![Single Cycle Processor](./Images/1-%20single-cycle-processor.png)



- **Multi Cycle Processor**: Contains the implementation of the multi-cycle RISC-V CPU and its modules.



![Multi Cycle Processor](./Images/2-%20multi-cycle-processor.png)



- **Pipelined Processor**: _Coming soon..._



![Pipelined Processor](./Images/3-%20pipelined-processor.png)



- **Images**: Visuals, diagrams, and waveform screenshots related to the design and simulation.

- **Resources**:

  - `Digital Design and Computer Architecture RISC-V Edition.pdf`

  - `Getting Started with FPGAs.pdf`

  - `Project Plan.pdf`

![Note](https://img.shields.io/badge/NOTE:-fb151a)

The `cpu.v` module is the top-level design and contains the instantiations of `datapath.v` and `control_unit.v`. These two modules further instantiate all the lower-level building blocks like the ALU, register file, memory, multiplexers, etc., to complete the processor architecture.

## Tools Used

- **Quartus Prime** – For writing, compiling, and deploying Verilog code.

- **ModelSim** – For simulation and debugging.

- **DE-1 SoC FPGA Board** – As the hardware target platform.

## Goal of the Project

The main objective is to understand and implement the internal working of a RISC-V CPU on an FPGA, focusing on datapath design, instruction decoding, and memory access.

## Related Work

If you're new to Verilog or want to brush up on the basics, check out this repo: [Getting Started with Verilog](https://github.com/Choaib-ELMADI/getting-started-with-verilog)