https://github.com/choaib-elmadi/riscv-on-de2-soc-fpga
A simplified RISC-V processor implemented in Verilog and deployed on the DE-2 SoC FPGA board.
https://github.com/choaib-elmadi/riscv-on-de2-soc-fpga
de2-board fpga fpga-board fpga-programming fpga-soc hdl processor programming risc risc-v riscv verilog
Last synced: 6 months ago
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A simplified RISC-V processor implemented in Verilog and deployed on the DE-2 SoC FPGA board.
- Host: GitHub
- URL: https://github.com/choaib-elmadi/riscv-on-de2-soc-fpga
- Owner: Choaib-ELMADI
- Created: 2025-04-05T14:53:33.000Z (8 months ago)
- Default Branch: master
- Last Pushed: 2025-06-14T21:02:12.000Z (6 months ago)
- Last Synced: 2025-06-14T22:18:50.523Z (6 months ago)
- Topics: de2-board, fpga, fpga-board, fpga-programming, fpga-soc, hdl, processor, programming, risc, risc-v, riscv, verilog
- Language: Verilog
- Homepage:
- Size: 24.4 MB
- Stars: 5
- Watchers: 1
- Forks: 2
- Open Issues: 0
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Metadata Files:
- Readme: README.md