https://github.com/cla7aye15i4nd/trivial-riscv-cpu

A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
https://github.com/cla7aye15i4nd/trivial-riscv-cpu

computer-architecture fpga pipeline riscv tomasulo-algorithm verilog-hdl

Last synced: 16 days ago
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A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.

• Host: GitHub
• URL: https://github.com/cla7aye15i4nd/trivial-riscv-cpu
• Owner: cla7aye15I4nd
• License: gpl-2.0
• Created: 2019-11-18T08:08:53.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2020-01-04T03:17:36.000Z (about 5 years ago)
• Last Synced: 2024-11-18T00:32:19.646Z (3 months ago)
• Topics: computer-architecture, fpga, pipeline, riscv, tomasulo-algorithm, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 4.85 MB
• Stars: 13
• Watchers: 1
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# trivial-riscv

This project is a trivial riscv cpu with tomasulo implemented in Verilog HDL, which is a course project of Computer Architecture, ACM Class @ SJTU.

> 越是强大的设计，有时可能会令人越痛苦																					

### Design

- name: ~~Error~~ **Isla**

- ISA: RISCV 32I

- tomasulo algorithm (out-of-order execution)

- 3-stages pipeline (fetch, dispatch, execute)

- 2-set associative 512B Instruction Cache (Replacing Policy: FIFO)

- IF Prefetch: Non-stop fetching instruction

- multiple ALU(Arithmetic Logic Unit)

- Segment LED timer, LED light game

- Direct map Data Cache

- Store Buffer

### Performance

- stably running on FPGA (200MHz, 81920 hours)

- IPC = analysing

### Todo

- [ ] Load buffer

- [ ] Instruction dual issue  

- [ ] Branch Prediction(BTB)

- [ ] Interactive IO

### Reference

- [RISC-V ISA Specification](http://riscv.org/specifications/)

- https://github.com/Evensgn/RISC-V-CPU (Memory Simulator)

- 雷思磊. 自己动手写 CPU. 电子工业出版社, 2014.

- John L. Hennessy, David A. Patterson, et al. Computer Architecture: A Quantitative Approach, Fifth Edition, 2012.