https://github.com/clementkim/logic-circuit-verilog

아주대학교 논리회로 - Verilog를 이용한 프로젝트 코드
https://github.com/clementkim/logic-circuit-verilog

logic-circuit verilog

Last synced: 4 days ago
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아주대학교 논리회로 - Verilog를 이용한 프로젝트 코드

• Host: GitHub
• URL: https://github.com/clementkim/logic-circuit-verilog
• Owner: ClementKim
• License: mit
• Created: 2024-11-30T14:08:40.000Z (2 months ago)
• Default Branch: main
• Last Pushed: 2024-11-30T14:13:23.000Z (2 months ago)
• Last Synced: 2024-12-15T18:17:38.022Z (about 2 months ago)
• Topics: logic-circuit, verilog
• Language: Verilog
• Homepage:
• Size: 2.93 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# logic-circuit-verilog