https://github.com/cloudypadmal/processor
https://github.com/cloudypadmal/processor
altera fpga process
Last synced: 16 days ago
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- Host: GitHub
- URL: https://github.com/cloudypadmal/processor
- Owner: CloudyPadmal
- Created: 2017-05-09T05:31:03.000Z (over 8 years ago)
- Default Branch: master
- Last Pushed: 2017-06-17T17:56:14.000Z (over 8 years ago)
- Last Synced: 2025-02-02T17:55:05.344Z (8 months ago)
- Topics: altera, fpga, process
- Language: Verilog
- Size: 44.1 MB
- Stars: 1
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Processor
Image processor using Altera DE FPGA
## Includes
- Matlab scripts to convert image to hex
- Python scripts to convert hex to mif
- Python scripts to convert hex to matlab.hex
- Matlab scripts to generate image from hex file
- Matlab scripts for mean square error calculations