https://github.com/coastalwhite/pulpino-top-level-cw305

The top-level Verilog files for the CW305 to run and communicate with the RISC-V PULPINO core
https://github.com/coastalwhite/pulpino-top-level-cw305

chipwhisperer pulpino riscv

Last synced: about 1 month ago
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The top-level Verilog files for the CW305 to run and communicate with the RISC-V PULPINO core

• Host: GitHub
• URL: https://github.com/coastalwhite/pulpino-top-level-cw305
• Owner: coastalwhite
• License: gpl-3.0
• Created: 2023-03-11T11:47:34.000Z (almost 2 years ago)
• Default Branch: main
• Last Pushed: 2024-03-19T10:37:47.000Z (9 months ago)
• Last Synced: 2024-10-14T03:04:59.262Z (2 months ago)
• Topics: chipwhisperer, pulpino, riscv
• Language: Verilog
• Homepage:
• Size: 303 KB
• Stars: 4
• Watchers: 1
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE
  • Citation: CITATION.cff

Awesome Lists containing this project

README

        
# Pulpino Top-Level CW305

A set of instructions, files and utilities to use the [PULPINO][pulpino] Risc-V

on a [ChipWhisperer 305][cw305] FPGA. This repository contains 4 main sections:

1. [Setup Instructions](setup/README.md)

2. [Programming Instructions](program/README.md)

3. [Modifications](modifications/README.md)

4. [Documentation](docs/README.md)

## Important Resources

This is a list of resources that was used during the production of this

repository and can contain information that is also useful for the users.

- [Pulpino Datasheet](https://pulp-platform.org/docs/pulpino_datasheet.pdf)

- [CV32E40P Documentation](https://cv32e40p.readthedocs.io/en/latest/)

- [Ibex Documentation](https://ibex-core.readthedocs.io/en/latest/)

## Contributions

If you find any mistakes or feel like you improved parts to this repository

which are useful to others, please consider contributing back to the

repository.

[pulpino]: https://github.com/pulp-platform/pulpino

[cw305]: https://www.newae.com/products/NAE-CW305