https://github.com/codenkoffee/clock-simulation

VHDL simulation of a digital clock for the CSEN605 course at the German University in Cairo. Includes clock generation and stimulus processes.
https://github.com/codenkoffee/clock-simulation

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VHDL simulation of a digital clock for the CSEN605 course at the German University in Cairo. Includes clock generation and stimulus processes.

• Host: GitHub
• URL: https://github.com/codenkoffee/clock-simulation
• Owner: CodeNKoffee
• Created: 2024-11-17T08:49:43.000Z (about 2 months ago)
• Default Branch: master
• Last Pushed: 2024-11-17T08:57:14.000Z (about 2 months ago)
• Last Synced: 2024-11-17T09:32:51.151Z (about 2 months ago)
• Topics: vhdl-code
• Language: VHDL
• Homepage:
• Size: 0 Bytes
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Digital Clock Simulation

This project is a VHDL simulation of a digital clock, created as part of the CSEN605 course at the German University in Cairo.

## Project Structure

- **Entity**: `digital_clock_tb`

- **Architecture**: `behavioral`

- **Signals**:

  - `clk`: Clock signal

  - `reset`: Reset signal

  - `seconds`: Seconds counter

  - `minutes`: Minutes counter

  - `hours`: Hours counter

- **Constants**:

  - `clk_period`: Clock period (adjustable for desired frequency)

## Processes

Clock Generation Process

Generates the clock signal by toggling `clk` every half period.

### Stimulus Process

Applies a reset signal for a few clock cycles and then lets the clock run indefinitely.

## Usage

To run the simulation, use a VHDL simulator such as ModelSim or GHDL. Load the digital_clock_tb entity and observe the behavior of the clock signals.

## License

This project is for educational purposes only and does not have a specific license.