https://github.com/coloquinte/locked-tapeout

Logic locking of a design build on TinyTapeout
https://github.com/coloquinte/locked-tapeout

Last synced: about 1 month ago
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Logic locking of a design build on TinyTapeout

• Host: GitHub
• URL: https://github.com/coloquinte/locked-tapeout
• Owner: Coloquinte
• License: apache-2.0
• Created: 2024-01-18T10:27:55.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2024-01-30T14:00:32.000Z (over 1 year ago)
• Last Synced: 2025-04-04T16:14:04.309Z (about 2 months ago)
• Language: Verilog
• Homepage:
• Size: 150 KB
• Stars: 4
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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# Locking a design using Moosic and TinyTapeout

![My Image](blog/locking.svg)

Logic locking is a way to secure silicon chips against supply chain attacks.

We wrote a Yosys plugin, [Moosic](https://github.com/Coloquinte/moosic-yosys-plugin), to apply logic locking solutions easily using a fully open source toolchain.

This is a showcase design to show how to apply logic locking on a simple example.

It uses [TinyTapeout](https://tinytapeout.com/) to go all the way to a silicon chip!

Have a look at the [blog post](https://blog.yosyshq.com/p/logic-locking-with-moosic/) on the YosysHQ blog for more information.

- [Read the documentation](docs/info.md)