https://github.com/cosminpopescu14/fpga

Sisteme FPGA
https://github.com/cosminpopescu14/fpga

fpga verilog

Last synced: 16 days ago
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Sisteme FPGA

• Host: GitHub
• URL: https://github.com/cosminpopescu14/fpga
• Owner: cosminpopescu14
• Created: 2014-08-07T15:30:49.000Z (over 10 years ago)
• Default Branch: master
• Last Pushed: 2014-11-01T15:55:47.000Z (about 10 years ago)
• Last Synced: 2024-05-18T07:41:59.372Z (8 months ago)
• Topics: fpga, verilog
• Language: Verilog
• Homepage:
• Size: 195 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
FPGA

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Sisteme FPGA, scoala de vara IPW

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Verilog

In folder-ul exercitii_fpga se gasesc exercitiile pe care le-am facut pe parcursul cursului. In folderul 'proiect' se gasesc fisierele pt proiecul final, "Controller UART pentru Nexys 3". Am invatat lucruri interesante pe perioada cursului. 

Voi actualiza coding style-ul si voi incerca sa aduc imbunatatiri. 

Pentru a utiliza codul este nevoie de un mediu de programare pt FPGA-uri cum ar fi Xilinx ISE, si un fisier de constrangeri. 

UART-http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter

Am lucrat impreuna cu colegul meu, Andrei Cristea