https://github.com/cpehle/cascade

Cycle based C++ hardware simulation infrastructure
https://github.com/cpehle/cascade

hardware simulation verilog

Last synced: 10 months ago
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Cycle based C++ hardware simulation infrastructure

• Host: GitHub
• URL: https://github.com/cpehle/cascade
• Owner: cpehle
• License: other
• Created: 2018-10-03T20:10:24.000Z (over 7 years ago)
• Default Branch: master
• Last Pushed: 2019-09-18T21:00:44.000Z (over 6 years ago)
• Last Synced: 2025-02-08T17:45:45.665Z (12 months ago)
• Topics: hardware, simulation, verilog
• Language: C++
• Homepage:
• Size: 1.65 MB
• Stars: 2
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README
  • License: LICENSE

Awesome Lists containing this project

README

          
       __________________________________________

C     /                                          

 A   /   Version 1.0 - March 10, 2013 

  S /                                            

   C     Copyright (c) 2013 D. E. Shaw Research  

  / A                                            

 /   D   All Rights Reserved                     

/     E__________________________________________

1. Supported compilers

   -------------------

This code requires some C++11 features and has been tested with the following compilers:

g++ 4.7.2

MSVC 2012

VCS 2010.06

The code is provided "as-is"; any other compiler or VCS version may require modifications.

2. Directories

   -----------

doc                    - documentation for Cascade and descore

examples/life          - Conway's game of life example from the Cascade manual

examples/adder_verilog - Cascade/Verilog co-simulation example

include                - Cascade/descore include files

msvc2012               - Visual studio 2012 solution

objs                   - Output directory for g++ builds

src                    - Cascade/descore source files

verilog                - Additional files required for Verilog co-simulation

3. Building and Running

   --------------------

Build descore:

$ cd src/descore

$ make

Build Cascade without support for Verilog co-simulation:

$ cd src/cascade

$ make

Build Cascade with support for Verilog co-simulation:

$ cd src/cascade

$ make verilog

Build and run life example (will automatically build descore and Cascade):

$ cd examples/life

$ make

$ life

Build and run adder_verilog example (will automatically build descore and Cascade):

$ cd examples/adder_verilog

$ make

$ simv

4. Contact information

   -------------------

Send all questions and suggestions to Cascade@DEShawResearch.com

Enjoy!