https://github.com/crambl/fpga-neuralnetwork

Fork of ZyNet (Based on work done here https://github.com/vipinkmenon/neuralNetwork) intended to be more modular and contain VHDL ports of Neuron models
https://github.com/crambl/fpga-neuralnetwork

Last synced: 3 months ago
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Fork of ZyNet (Based on work done here https://github.com/vipinkmenon/neuralNetwork) intended to be more modular and contain VHDL ports of Neuron models

• Host: GitHub
• URL: https://github.com/crambl/fpga-neuralnetwork
• Owner: CramBL
• License: mit
• Created: 2023-04-13T14:49:31.000Z (about 2 years ago)
• Default Branch: main
• Last Pushed: 2023-07-28T17:25:14.000Z (almost 2 years ago)
• Last Synced: 2025-01-23T04:33:04.274Z (5 months ago)
• Language: Tcl
• Homepage:
• Size: 45.3 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: MIT-LICENSE

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README

        
Fork of ZyNet (Based on work done here https://github.com/vipinkmenon/neuralNetwork) intended to be more modular and contain VHDL ports of Neuron models .

## Adjust weights, activation function etc.

Use the `mnistZyNet.py` script

```shell

$ python mnistZyNet.py --help

```

## Example performance

Sigmoid size is the width in bits of the values in the LUT for the sigmoid function, meaning how many steps the sigmoid function is divided into. More bits means smaller steps, means smaller disparity between the discretized value and the actual value of the function.

| Sigmoid Size [bits] | 2   | 3   | 4    | 5    | 6    | 7   | 8    | 9    | 10   |

| ------------------- | --- | --- | ---- | ---- | ---- | --- | ---- | ---- | ---- |

| Accuracy [%]        | 8.5 | 8.5 | 11.6 | 94.1 | 94.5 | 95  | 95.1 | 95.1 | 95.1 |

![sigsize-vs-accuracy](plots/sig-size-acc.svg)