https://github.com/cryptape/rvv-encoder

RISC-V V Extension Encoder
https://github.com/cryptape/rvv-encoder

assembly encode riscv vector

Last synced: 20 days ago
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RISC-V V Extension Encoder

• Host: GitHub
• URL: https://github.com/cryptape/rvv-encoder
• Owner: cryptape
• Created: 2022-01-04T07:43:09.000Z (almost 3 years ago)
• Default Branch: master
• Last Pushed: 2022-07-28T06:13:31.000Z (over 2 years ago)
• Last Synced: 2024-04-17T14:19:34.627Z (8 months ago)
• Topics: assembly, encode, riscv, vector
• Language: Rust
• Homepage:
• Size: 116 KB
• Stars: 11
• Watchers: 3
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        

# RVV encoder

* `rvv-encode` - A Library to encode RISC-V V extension instruction

* `rvv-asm` - A procedure macro to encode RISC-V V extension instructions

* `rvv-as` - A command line tool to encode RISC-V V extension instructions

## `rvv-asm` example

```rust

unsafe {

    rvv_asm::rvv_asm!(

        "vsetvl x5, s3, t6",

        "1: vle256.v v3, (a0), vm",

        "2:",

        "li {lo}, 4",

        lo = out(reg) lo,

    );

}

```

## `rvv-as` usage

```

USAGE:

    rvv-as [OPTIONS] 

ARGS:

        The original assembly source file path

OPTIONS:

    -c, --comment-origin                     Use original instruction and its code as comment

    -p, --comment-prefix     The comment prefix [default: #]

    -r, --reserved-only                      Only translate reserved rvv instructions

```