https://github.com/cw1997/verilog-parser

Verilog HDL Parser
https://github.com/cw1997/verilog-parser

parser parsers verilog verilog-hdl verilog-simulator

Last synced: about 2 months ago
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Verilog HDL Parser

• Host: GitHub
• URL: https://github.com/cw1997/verilog-parser
• Owner: cw1997
• License: apache-2.0
• Created: 2021-06-09T08:15:06.000Z (over 4 years ago)
• Default Branch: main
• Last Pushed: 2021-06-14T20:36:13.000Z (over 4 years ago)
• Last Synced: 2025-03-22T07:17:57.630Z (9 months ago)
• Topics: parser, parsers, verilog, verilog-hdl, verilog-simulator
• Language: ANTLR
• Homepage:
• Size: 38.1 KB
• Stars: 4
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# verilog-parser

VerilogHDL Parser