https://github.com/danielvieiravega/vcdparser
Value Change Dump (VCD) File parser
https://github.com/danielvieiravega/vcdparser
hdl simulations value-change-dump vcd verilog vhdl
Last synced: about 1 month ago
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Value Change Dump (VCD) File parser
- Host: GitHub
- URL: https://github.com/danielvieiravega/vcdparser
- Owner: danielvieiravega
- Created: 2017-04-12T16:35:13.000Z (about 8 years ago)
- Default Branch: master
- Last Pushed: 2017-05-21T02:02:56.000Z (about 8 years ago)
- Last Synced: 2025-03-27T18:13:53.353Z (about 2 months ago)
- Topics: hdl, simulations, value-change-dump, vcd, verilog, vhdl
- Language: C++
- Homepage:
- Size: 145 KB
- Stars: 7
- Watchers: 2
- Forks: 1
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Value Change Dump (VCD) File
A value change dump (VCD) file logs changes to variable values, such as the values of signals, in a file during a simulation session. VCD files can be useful during design verification. Some examples of how you might apply VCD files include the following cases:
- For comparing results of multiple simulation runs, using the same or different simulator environments
- As input to post-simulation analysis tools
- For porting areas of an existing design to a new design
VCD files can provide data that you might not otherwise acquire unless you understood the details of a device's internal logic. In addition, they include data that can be graphically displayed or analyzed with postprocessing tools, including, for example, the extraction of data about a particular section of a design hierarchy or data generated during a specific time interval.
This parser show useful data from the simulation like all modules, signals, signals switching activity, clock frequency, simulation date and simulation tool version.