https://github.com/davidf1000/sistemdigital_vhdl

Final Project for Digital System Lab. Flappy Bird Imitation Game created using VHDL for FPGA DE1.
https://github.com/davidf1000/sistemdigital_vhdl

fpga quartus verilog vhdl

Last synced: 5 months ago
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Final Project for Digital System Lab. Flappy Bird Imitation Game created using VHDL for FPGA DE1.

• Host: GitHub
• URL: https://github.com/davidf1000/sistemdigital_vhdl
• Owner: davidf1000
• Created: 2019-11-16T15:10:05.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2021-02-08T15:37:34.000Z (over 5 years ago)
• Last Synced: 2025-06-03T18:43:17.432Z (about 1 year ago)
• Topics: fpga, quartus, verilog, vhdl
• Language: VHDL
• Homepage:
• Size: 1.33 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# SistemDigital_VHDL

Tugas Besar Lab Sistem Digital , membuat imitasi game flappy bird menggunakan VHDL pada software Quartus yang dijalankan pada FPGA. 

![1001091](https://user-images.githubusercontent.com/47879766/107242083-34309000-6a5e-11eb-868d-d926aeab0b3b.jpg)

![1001089](https://user-images.githubusercontent.com/47879766/107242091-3561bd00-6a5e-11eb-9908-4d417aae89ba.jpg)

![1001090](https://user-images.githubusercontent.com/47879766/107242092-3561bd00-6a5e-11eb-9803-0374b3721f17.jpg)