https://github.com/defparam/higan-verilog
This is a higan/Verilator co-simulation example/framework
https://github.com/defparam/higan-verilog
emulation emulator fpga simulation snes snes-programming verilog verilog-hdl
Last synced: 6 months ago
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This is a higan/Verilator co-simulation example/framework
- Host: GitHub
- URL: https://github.com/defparam/higan-verilog
- Owner: defparam
- License: other
- Created: 2018-04-04T23:03:01.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2018-04-17T14:52:14.000Z (over 7 years ago)
- Last Synced: 2025-04-09T22:16:37.232Z (6 months ago)
- Topics: emulation, emulator, fpga, simulation, snes, snes-programming, verilog, verilog-hdl
- Language: C++
- Size: 1.36 MB
- Stars: 50
- Watchers: 5
- Forks: 7
- Open Issues: 0