https://github.com/defparam/higan-verilog

This is a higan/Verilator co-simulation example/framework
https://github.com/defparam/higan-verilog

emulation emulator fpga simulation snes snes-programming verilog verilog-hdl

Last synced: 29 days ago
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This is a higan/Verilator co-simulation example/framework

• Host: GitHub
• URL: https://github.com/defparam/higan-verilog
• Owner: defparam
• License: other
• Created: 2018-04-04T23:03:01.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2018-04-17T14:52:14.000Z (over 6 years ago)
• Last Synced: 2023-03-02T17:41:40.406Z (almost 2 years ago)
• Topics: emulation, emulator, fpga, simulation, snes, snes-programming, verilog, verilog-hdl
• Language: C++
• Size: 1.36 MB
• Stars: 43
• Watchers: 5
• Forks: 6
• Open Issues: 0

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