https://github.com/democrito/ads7924

This module is a block that reads the 4 ADC inputs of the ADS7924 and presents the results as plain four 12-bit values.
https://github.com/democrito/ads7924

Last synced: 12 days ago
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This module is a block that reads the 4 ADC inputs of the ADS7924 and presents the results as plain four 12-bit values.

• Host: GitHub
• URL: https://github.com/democrito/ads7924
• Owner: Democrito
• Created: 2024-07-06T20:48:06.000Z (6 months ago)
• Default Branch: main
• Last Pushed: 2024-08-22T10:52:11.000Z (5 months ago)
• Last Synced: 2024-08-22T12:19:35.047Z (5 months ago)
• Size: 50.8 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# ADS7924

### [Icestudio](https://github.com/FPGAwars/icestudio) / FPGA

This module is a block that reads the 4 ADC inputs of the ADS7924 and presents the results as plain four 12-bit values. Additionally, a simple example has been added for immediate implementation.

More info and more versions in pure Verilog: https://groups.google.com/g/fpga-wars-explorando-el-lado-libre/c/9gcu-SFjloA

The digital electronic design of the **ADS7924** reader module belongs to **[Jesús Arias](https://www.ele.uva.es/~jesus/)**.