https://github.com/dessaya/tp-clp

https://github.com/dessaya/tp-clp

Last synced: 10 days ago
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• Host: GitHub
• URL: https://github.com/dessaya/tp-clp
• Owner: dessaya
• Created: 2020-05-25T19:37:57.000Z (over 4 years ago)
• Default Branch: master
• Last Pushed: 2020-06-05T17:44:43.000Z (over 4 years ago)
• Last Synced: 2024-10-25T15:38:42.028Z (about 2 months ago)
• Language: VHDL
• Size: 4 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
Para ejecutar las simulaciones (Requiere GHDL y GTKWave):

* Componente `adder1`: `make -f Makefile.adder1`

* Componente `addern`: `make -f Makefile.addern`

* Componente `mul`: `make -f Makefile.mul`

* Componente `fpmul`: `make`

Para correr los tests: `make test` (configurar `WORD_SIZE_T` y `EXP_SIZE_T`

en `fpmul_tb.vhd`) para utilizar el archivo correspondiente en la carpeta `test-files`.

Presentación: https://docs.google.com/presentation/d/1DSy83k4kNMWb_fBu7IstFsx7bWicQSvUaGacOdMYWCg/edit?usp=sharing