https://github.com/diffblue/hw-cbmc
The HW-CBMC and EBMC Model Checkers for Verilog
https://github.com/diffblue/hw-cbmc
Last synced: 3 months ago
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The HW-CBMC and EBMC Model Checkers for Verilog
- Host: GitHub
- URL: https://github.com/diffblue/hw-cbmc
- Owner: diffblue
- License: other
- Created: 2017-05-01T13:43:59.000Z (about 8 years ago)
- Default Branch: main
- Last Pushed: 2025-04-18T19:59:19.000Z (3 months ago)
- Last Synced: 2025-04-19T03:30:08.817Z (3 months ago)
- Language: C++
- Homepage:
- Size: 4.67 MB
- Stars: 66
- Watchers: 8
- Forks: 18
- Open Issues: 66
-
Metadata Files:
- Readme: README.md
- Changelog: CHANGELOG
- License: LICENSE
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README
About
=======
EBMC is a bounded model checker for the Verilog language (and other HW
specification languages). The verification is performed by synthesizing a
transition system from the Verilog, unwinding the transition system (up to a
certain bound), and then producing a decision problem. The decision problem
encodes the circuit and the negation of the property under verification.
Hence if satisfiable, the tool produces a counterexample demonstrating
violation of the property. EBMC can use CBMC's bit-vector solver or Z3
or CVC4 to solve the decision problem.
For full information see [cprover.org](http://www.cprover.org/ebmc/).
Usage
=====
Let us assume we have the following SystemVerilog code in `main.sv`.
```main.sv
module main(input clk, x, y);
reg [1:0] cnt1;
reg z;
initial cnt1=0;
initial z=0;
always @(posedge clk) cnt1=cnt1+1;
always @(posedge clk)
casex (cnt1)
2'b00:;
2'b01:;
2'b1?: z=1;
endcase
p1: assert property (@(posedge clk) (z==0));
endmodule
```
Then we can run the EBMC verification as
`$> ebmc main.sv --module main --bound 3`
setting the unwinding bound to `3` and running the verification of the module `main`.
For more information see [EBMC Manual](http://www.cprover.org/ebmc/manual/)