https://github.com/dilawar/pyghdl

A python frontend for ghdl
https://github.com/dilawar/pyghdl

Last synced: about 2 months ago
JSON representation

A python frontend for ghdl

• Host: GitHub
• URL: https://github.com/dilawar/pyghdl
• Owner: dilawar
• Created: 2013-03-07T10:44:08.000Z (almost 12 years ago)
• Default Branch: master
• Last Pushed: 2014-04-19T05:23:08.000Z (over 10 years ago)
• Last Synced: 2023-03-22T15:28:30.705Z (almost 2 years ago)
• Language: VHDL
• Size: 880 KB
• Stars: 0
• Watchers: 0
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.rst

Awesome Lists containing this project

README

        
pyghdl

======

A python front-end for ghdl/vsim.  Simulator vsim is not supported yet.

-  Search for top-most modules in given design and compile it using ghdl.

-  Look for in and out ports and generate a test-bench (if not written). 

-  Do something cool in test-bench. (Yet not finished)

After installing, the binary name is `hdl2tb.py`.