https://github.com/djg/cpu

CPU - Verilog + Rust
https://github.com/djg/cpu

cmake fpga rtl rust verilator verilog

Last synced: 15 days ago
JSON representation

CPU - Verilog + Rust

• Host: GitHub
• URL: https://github.com/djg/cpu
• Owner: djg
• Created: 2018-03-05T02:44:27.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2018-03-05T02:44:52.000Z (over 6 years ago)
• Last Synced: 2023-03-12T06:53:45.655Z (over 1 year ago)
• Topics: cmake, fpga, rtl, rust, verilator, verilog
• Language: CMake
• Homepage:
• Size: 14.6 KB
• Stars: 2
• Watchers: 2
• Forks: 1
• Open Issues: 0

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