https://github.com/djg/cpu

CPU - Verilog + Rust
https://github.com/djg/cpu

cmake fpga rtl rust verilator verilog

Last synced: 20 days ago
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CPU - Verilog + Rust

• Host: GitHub
• URL: https://github.com/djg/cpu
• Owner: djg
• Created: 2018-03-05T02:44:27.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2018-03-05T02:44:52.000Z (almost 7 years ago)
• Last Synced: 2024-11-01T05:26:28.549Z (2 months ago)
• Topics: cmake, fpga, rtl, rust, verilator, verilog
• Language: CMake
• Homepage:
• Size: 14.6 KB
• Stars: 2
• Watchers: 3
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# CPU - Verilog + Rust

Inspired by [yupferris](https://www.youtube.com/watch?v=MSWyQJO0ho0)

xenowing project, this is a crazy hydra project of `rust`, `c++`, and

`verilog` driven by `Cargo` and `cmake`.

Most of the `cmake` heavy lifting comes from the

[logic](https://github.com/tymonx/logic) project, although I modifed

the `verilator` support to use `cmake` instead of `make` to compile.

The `test_bench` crate is based upon [looking at

verilator](http://zipcpu.com/blog/2017/06/21/looking-at-verilator.html)

blog by ZipCPU.