https://github.com/dkm/tivarust

https://github.com/dkm/tivarust

bare-metal cortex-m rust tiva-c-series

Last synced: 25 days ago
JSON representation

• Host: GitHub
• URL: https://github.com/dkm/tivarust
• Owner: dkm
• License: other
• Created: 2017-02-17T19:09:30.000Z (almost 8 years ago)
• Default Branch: master
• Last Pushed: 2017-04-14T21:50:33.000Z (over 7 years ago)
• Last Synced: 2024-10-28T00:01:58.267Z (2 months ago)
• Topics: bare-metal, cortex-m, rust, tiva-c-series
• Language: Rust
• Size: 75.2 KB
• Stars: 0
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# tivarust: Small pet project to learn Rust and low level ARM

## Setting up environment

Install rustup, rust nightly and xargo: https://github.com/japaric/xargo

## Building

```

$ PATH=$HOME/.cargo/bin:$PATH make all

```

## Debuging using openocd

### Running openocd & GDB

```

$ make debug

```

### Using python extension to inspect low level registers

```

(gdb) source gdb.py

(gdb) read-tiva

RCC : 0x01CE1540 @ 0x400FE060

  > Main oscillator ENABLED

  > Oscillator source: [MOSC] Main Oscillator

  > [XTAL] Crystal value 16.0 Mhz

  > [BYPASS] The system clock is the PLL output divided by SYSDIV

  > PLL is operating normally

  > [PWMDIV] PWM Unit Clock Divisor is 64

  > [USEPWMDIV] PWM Clock Divisor : The system clock divider is the source for PWM

  > [USESYSDIV] Enable System Clock Divider: system clock divider is used (forced when PLL is selected as the source)

  > [SYSDIV] System Clock Divisor: 3

  > [ACG] Auto Clock Gating: RCGCn registers are used

...

```