https://github.com/dmoore12/sv-sim
A simple SystemVerilog simulation tool written in rust
https://github.com/dmoore12/sv-sim
systemverilog systemverilog-simulation systemverilog-test-bench
Last synced: 2 months ago
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A simple SystemVerilog simulation tool written in rust
- Host: GitHub
- URL: https://github.com/dmoore12/sv-sim
- Owner: DMoore12
- License: mit
- Created: 2024-08-23T03:03:00.000Z (about 1 year ago)
- Default Branch: main
- Last Pushed: 2024-08-25T21:43:25.000Z (about 1 year ago)
- Last Synced: 2024-10-31T11:40:17.030Z (about 1 year ago)
- Topics: systemverilog, systemverilog-simulation, systemverilog-test-bench
- Language: Rust
- Homepage:
- Size: 837 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# SystemVerilog Simulation
_A simple SystemVerilog simulation tool written in rust_
> This project is in a very early state
## Project Scope
- [X] Provide an incomplete, slightly broken SystemVerilog parser
- [ ] Provide a simple SystemVerilog parser
- [ ] Provide simple analysis tools
- [ ] Allow design verification for simple projects
## Repository Contents
- [src](https://github.com/DMoore12/sv-sim/tree/main/src): source files
- [sv](https://github.com/DMoore12/sv-sim/tree/main/sv): example SystemVerilog files for testing
## Installation
**sv-sim** uses `cargo` for package management. If you wish to generate documentation with styling, `generate_docs.sh` is provided. In order to apply styling, git submodules must be initialized.
```shell
# Clone repo
git clone https://github.com/DMoore12/sv-sim.git
# Initialize submodules
cd ./sv-sim
git submodule init
# Run test file
cargo run -- ./sv/cu_top.sv none
# Generate documentation
sudo chmod +x generate_docs.sh
./generate_docs.sh
```
## Usage
**sv-sim** uses `clap` for argument parsing. Use `cargo run -- --help` or `sv-sim[EXE] --help` to view input arguments and parameters
### Arguments
- `log_level`
- Log level for output. Defaults to `error`
- `verbose`
- Gives additional build information in output