https://github.com/doctorwkt/2fisc

FISC2: A TTL CPU with Some 16-bit Capabilities
https://github.com/doctorwkt/2fisc

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FISC2: A TTL CPU with Some 16-bit Capabilities

• Host: GitHub
• URL: https://github.com/doctorwkt/2fisc
• Owner: DoctorWkt
• License: gpl-3.0
• Created: 2020-06-30T12:19:18.000Z (almost 5 years ago)
• Default Branch: master
• Last Pushed: 2020-07-11T07:12:36.000Z (almost 5 years ago)
• Last Synced: 2025-03-31T07:51:15.240Z (3 months ago)
• Language: Perl
• Size: 6.46 MB
• Stars: 10
• Watchers: 4
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# FISC2: A TTL CPU with Some 16-bit Capabilities

FISC2 is a microseqenced CPU built from discrete TTL-level components.

It provides

 + recursive **F**unctions,

 + **I**ndexed addressing,

 + **S**tack operations, and

 + some instructions on 16-bit data values

as well as the usual load/store and arithmetic operations, comparisons,

branches and jumps.

The design uses 29 chips and has 8K of ROM, 336K of available RAM and a UART.

![](Docs/Figs/pcb.jpg)

## Documentation

The overall design of the CPU is covered in

[Docs/arch_overview.md](Docs/arch_overview.md), and some details

of the hardware implementation are in 

[Docs/fisc2_implementation.md](Docs/fisc2_implementation.md).

## Implementation

At present, I have:

 + a Perl CPU simulator, [csim](csim)

 + an assembler, [cas](cas)

 + a simple compiler, [clc](clc)

 + example assembly and higher-level programs in [Examples](Examples)

 + a Verilog design in [Verilog](Verilog)

 + a final schematic in [Kicad/schematic.pdf](Kicad/schematic.pdf)

## Status of the CPU

**early-July, 2020**: Both the Perl simulator and the Verilog model work

well. I am happy with the design and I've ordered the PCBs and components.

For more detail on progress, you can read my [journal](Docs/journal.md).