https://github.com/doctorwkt/fisc
An 8-bit TTL CPU with a Stack Pointer
https://github.com/doctorwkt/fisc
Last synced: about 1 month ago
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An 8-bit TTL CPU with a Stack Pointer
- Host: GitHub
- URL: https://github.com/doctorwkt/fisc
- Owner: DoctorWkt
- License: gpl-3.0
- Created: 2020-05-16T01:01:58.000Z (about 5 years ago)
- Default Branch: master
- Last Pushed: 2020-07-05T05:44:33.000Z (almost 5 years ago)
- Last Synced: 2025-03-31T07:51:12.786Z (3 months ago)
- Language: Perl
- Size: 6.98 MB
- Stars: 6
- Watchers: 2
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# FISC: An 8-bit TTL CPU with a Stack Register
**Please note**: The FISC design has some major flaws. Rather than
fix them, I've incorporated the fixes into the next version of the
design: .
FISC is an 8-bit microseqenced CPU wth a 64K address space built from
discrete TTL-level components. It provides:
+ recursive **F**unctions,
+ **I**ndexed addressing and
+ **S**tack operations
as well as the usual load/store and arithmetic operations, comparisons,
branches and jumps.
The design uses 25 chips and has 8K of ROM, 56K of RAM and a UART.
## Documentation
The overall design of the CPU is covered in
[Docs/arch_overview.md](Docs/arch_overview.md), and some details
of the expected hardware implementation are in
[Docs/fisc_implementation.md](Docs/fisc_implementation.md).
## Implementation
At present, I have:
+ a Perl CPU simulator, [csim](csim)
+ an assembler, [cas](cas)
+ a simple compiler, [clc](clc)
+ example assembly and higher-level programs in [Examples](Examples)
+ a Verilog design in [Verilog](Verilog)
+ a schematic in [Kicad/schematic.pdf](Kicad/schematic.pdf)
## Status of the CPU
**mid-June, 2020**: I've ordered PCBs and they have arrived and I've soldered
on all the components. The CPU passes most of the tests but I have an issue
with addition that I am still working on.
For more detail on progress, you can read my [journal](Docs/journal.md).