https://github.com/doniagameel/pipelined-processor-using-verilog
Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
https://github.com/doniagameel/pipelined-processor-using-verilog
alu assembler branch-prediction control-unit full-forwarding hazard-detection pipelined-processors
Last synced: about 1 year ago
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Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
- Host: GitHub
- URL: https://github.com/doniagameel/pipelined-processor-using-verilog
- Owner: DoniaGameel
- Created: 2023-01-28T22:23:04.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2023-01-29T17:13:42.000Z (over 3 years ago)
- Last Synced: 2025-02-13T05:48:20.758Z (over 1 year ago)
- Topics: alu, assembler, branch-prediction, control-unit, full-forwarding, hazard-detection, pipelined-processors
- Language: Verilog
- Homepage:
- Size: 891 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0