https://github.com/doniagameel/verilog-adders-with-synthesis-using-oasys
explore different implementations of adders and study their characteristics.
https://github.com/doniagameel/verilog-adders-with-synthesis-using-oasys
carry-bypass-adder carry-increment-adder carry-look-ahead-adder carry-save-adder carry-select-adder carry-skip-adder floating-point-adder oasys ripple-carry-adder
Last synced: about 2 months ago
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explore different implementations of adders and study their characteristics.
- Host: GitHub
- URL: https://github.com/doniagameel/verilog-adders-with-synthesis-using-oasys
- Owner: DoniaGameel
- Created: 2023-01-26T13:17:00.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2024-05-23T21:25:22.000Z (12 months ago)
- Last Synced: 2025-02-13T05:48:20.030Z (3 months ago)
- Topics: carry-bypass-adder, carry-increment-adder, carry-look-ahead-adder, carry-save-adder, carry-select-adder, carry-skip-adder, floating-point-adder, oasys, ripple-carry-adder
- Language: Verilog
- Homepage:
- Size: 670 KB
- Stars: 2
- Watchers: 1
- Forks: 4
- Open Issues: 0