https://github.com/drom/atom-hide

Atom Hardware IDE
https://github.com/drom/atom-hide

Last synced: about 1 year ago
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Atom Hardware IDE

• Host: GitHub
• URL: https://github.com/drom/atom-hide
• Owner: drom
• License: mit
• Created: 2019-06-26T21:26:01.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2021-05-04T15:04:09.000Z (about 5 years ago)
• Last Synced: 2025-04-15T03:04:08.742Z (about 1 year ago)
• Language: JavaScript
• Homepage:
• Size: 67.4 KB
• Stars: 13
• Watchers: 3
• Forks: 0
• Open Issues: 2
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

          


[![Version!](https://img.shields.io/apm/v/hide.svg?style=flat-square)](https://atom.io/packages/hide)

[![Linux](https://github.com/drom/atom-hide/actions/workflows/linux.yml/badge.svg)](https://github.com/drom/atom-hide/actions/workflows/linux.yml)

[![MacOS](https://github.com/drom/atom-hide/actions/workflows/macos.yml/badge.svg)](https://github.com/drom/atom-hide/actions/workflows/macos.yml)

[![Windows](https://github.com/drom/atom-hide/actions/workflows/windows.yml/badge.svg)](https://github.com/drom/atom-hide/actions/workflows/windows.yml)

Hardware Integrated Development Environment (hide)

### Install

```

apm i hide

```

### Features

* Based on [Atom text editor](https://atom.io)

* Source Editor Panel

  - Verilog / SyetemVeilog

    * [Tree Sitter Verilog](https://github.com/tree-sitter/tree-sitter-verilog)

      - Syntax highlighting

      - Code folding

      - Linter using [svlint](https://github.com/drom/svlint)

      - Diagnostics (errors, warnings)

  - FIRRTL

    * [Tree Sitter FIRRTL](https://github.com/chipsalliance/tree-sitter-firrtl)

      - Syntax highlighting

      - Diagnostics (errors, warnings)

  - SystemRDL

    * [Tree Sitter SystemRDL](https://github.com/SystemRDL/tree-sitter-systemrdl)

      - Syntax highlighting

      - Diagnostics (errors, warnings)

### TODO

* Source Editor Panel

  - Verilog / SyetemVeilog

    * Better Code folding

    * Auto-complete

    * Go to definition

    * Find references

    * Format source code

    * Type information on hover

    * Find references

    * [Verilog mode](https://www.veripool.org/wiki/verilog-mode)

  - VHDL

* Waveform Panel

  - [Wavedrom Zoom](https://github.com/wavedrom/zoom)

* Logic Schematic Panel

  - RTL viewer

* Outline view