https://github.com/dyna-bytes/fisr

Specialized FPU for Fast Inverse Square Root Algorithm
https://github.com/dyna-bytes/fisr

floating-point fpu hardware-acceleration verilog

Last synced: 3 days ago
JSON representation

Specialized FPU for Fast Inverse Square Root Algorithm

• Host: GitHub
• URL: https://github.com/dyna-bytes/fisr
• Owner: dyna-bytes
• Created: 2022-03-21T05:00:48.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2022-11-10T03:24:23.000Z (about 2 years ago)
• Last Synced: 2024-12-02T21:11:44.260Z (2 months ago)
• Topics: floating-point, fpu, hardware-acceleration, verilog
• Language: Verilog
• Homepage:
• Size: 1010 KB
• Stars: 1
• Watchers: 1
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
# FISR

Specialized FPU for Fast Inverse Square Root Algorithm

----

Got inspired from this [video](https://www.youtube.com/watch?v=p8u_k2LIZyo)!  

I might think it would be easy to understand what we did if you watch the above video. 

FISR algorithm computes the inverse square root( $y = {{1}\over {\sqrt x}}$ ) 4 times faster than traditional methods with IEEE floating point tricks.  

We have succeeded in implementing this algorithm as digital circuits using Verilog. Hope you enjoy viewing our work!