https://github.com/efabless/frigate_analog
The analog signal processing and timing frontend subsystems for the Frigate harness chip
https://github.com/efabless/frigate_analog
Last synced: 4 months ago
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The analog signal processing and timing frontend subsystems for the Frigate harness chip
- Host: GitHub
- URL: https://github.com/efabless/frigate_analog
- Owner: efabless
- License: apache-2.0
- Created: 2025-02-14T14:20:06.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2025-02-25T14:38:36.000Z (over 1 year ago)
- Last Synced: 2025-02-25T15:35:21.882Z (over 1 year ago)
- Language: Verilog
- Size: 7.25 MB
- Stars: 0
- Watchers: 4
- Forks: 0
- Open Issues: 2
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Metadata Files:
- Readme: README
- License: LICENSE