https://github.com/efabless/sky130_sram_macros_old

https://github.com/efabless/sky130_sram_macros_old

Last synced: 4 months ago
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• Host: GitHub
• URL: https://github.com/efabless/sky130_sram_macros_old
• Owner: efabless
• License: apache-2.0
• Created: 2020-11-27T19:02:02.000Z (over 5 years ago)
• Default Branch: main
• Last Pushed: 2022-07-11T10:04:23.000Z (almost 4 years ago)
• Last Synced: 2024-08-10T14:17:32.446Z (almost 2 years ago)
• Language: SourcePawn
• Size: 180 MB
• Stars: 36
• Watchers: 9
• Forks: 19
• Open Issues: 4
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# SKY130 Standard SRAM configurations

This directory contains configurations for the standard SRAM configurations

that are generated.

They fall into the following categories;

 * Single port with byte write SRAM suitable for RISC-V and other processor

   main memory.

 * Pseudo-dual port SRAM (one write, one read) suitable for FIFOs.

 * True dual port SRAM (two read/write ports) suitable for high speed data

   sharing between two devices.

 * Dual access SRAM (one read/write, one read port) suitable for applications

   which need to read two data values every cycle (such as register files).

Currently supported sizes are 1kbytes, 2kbytes and 4kbytes. Larger arrays will

be supported in the future.

As the OpenRAM memory generator is freely available, you can also generate

memories of your own configuration and are not restricted to these pre-built

memory configurations.