https://github.com/eimon96/vhdl

https://github.com/eimon96/vhdl

logic-gates vhdl vhdl-code vhdl-coursework vhdl-testbench

Last synced: about 1 month ago
JSON representation

• Host: GitHub
• URL: https://github.com/eimon96/vhdl
• Owner: eimon96
• Created: 2021-01-17T15:30:42.000Z (over 4 years ago)
• Default Branch: main
• Last Pushed: 2021-02-22T21:04:57.000Z (about 4 years ago)
• Last Synced: 2025-01-20T15:18:24.575Z (3 months ago)
• Topics: logic-gates, vhdl, vhdl-code, vhdl-coursework, vhdl-testbench
• Language: VHDL
• Homepage:
• Size: 342 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
Basic logic gates implementations using 

VHDL Simili 3.1 (Symphony EDA Sonata 3.1) 

(win64)

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Furthermore:

D Flip Flop-schematic:

![](https://i.imgur.com/tWW3c35.png)

T Flip Flop-schematic:

![](https://i.imgur.com/UvqZKIv.png)

https://www.multisim.com/contributors/574827-eimon96/