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https://github.com/ellisgl/addressable-debouncer-verilog

Addressable 8 SPDT debouncer in Verilog
https://github.com/ellisgl/addressable-debouncer-verilog

cpld debounce debounce-button debouncing fpga verilog

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Addressable 8 SPDT debouncer in Verilog

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Addressable 8 SPDT Debouncer in Verilog
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An addressable debouncer for use with a CPLD / FPGA.

EDA Playground: https://www.edaplayground.com/x/64qZ

### Features
* Debounces 8 SPDT buttons.
* Addressable with 3 bit (Giving you 8 devices, or 64 total buttons).

### Notes
* Button ports should be set for pull-up.
* Button common should be connected to ground.
* N.C. should be connected to S(et) and N.O. to R(eset), so N.C. to port 0, and N.O. to port 1, and so on.
* Address select ports should be set for pull-up, connect to ground for "1".
* Address bus is just a normal TTL, 1 = 1.

### Todo
* individual folders for different CPLD/FPGAs (Verilog + Constraints and Schematics). This will be limited to what I have available.