https://github.com/ellisgl/addressable-debouncer-verilog

Addressable 8 SPDT debouncer in Verilog
https://github.com/ellisgl/addressable-debouncer-verilog

cpld debounce debounce-button debouncing fpga verilog

Last synced: 2 days ago
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Addressable 8 SPDT debouncer in Verilog

• Host: GitHub
• URL: https://github.com/ellisgl/addressable-debouncer-verilog
• Owner: ellisgl
• License: bsd-3-clause
• Created: 2018-05-28T04:30:45.000Z (over 6 years ago)
• Default Branch: release
• Last Pushed: 2020-06-28T03:14:49.000Z (over 4 years ago)
• Last Synced: 2024-11-18T22:13:50.226Z (2 months ago)
• Topics: cpld, debounce, debounce-button, debouncing, fpga, verilog
• Language: Verilog
• Size: 15.6 KB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0

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