https://github.com/ellisgl/addressable-debouncer-verilog
Addressable 8 SPDT debouncer in Verilog
https://github.com/ellisgl/addressable-debouncer-verilog
cpld debounce debounce-button debouncing fpga verilog
Last synced: 3 months ago
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Addressable 8 SPDT debouncer in Verilog
- Host: GitHub
- URL: https://github.com/ellisgl/addressable-debouncer-verilog
- Owner: ellisgl
- License: bsd-3-clause
- Created: 2018-05-28T04:30:45.000Z (about 7 years ago)
- Default Branch: release
- Last Pushed: 2020-06-28T03:14:49.000Z (almost 5 years ago)
- Last Synced: 2025-01-19T19:57:36.419Z (5 months ago)
- Topics: cpld, debounce, debounce-button, debouncing, fpga, verilog
- Language: Verilog
- Size: 15.6 KB
- Stars: 1
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE.BSD
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README
Addressable 8 SPDT Debouncer in Verilog
=====================================================
An addressable debouncer for use with a CPLD / FPGA.
EDA Playground: https://www.edaplayground.com/x/64qZ
### Features
* Debounces 8 SPDT buttons.
* Addressable with 3 bit (Giving you 8 devices, or 64 total buttons).
### Notes
* Button ports should be set for pull-up.
* Button common should be connected to ground.
* N.C. should be connected to S(et) and N.O. to R(eset), so N.C. to port 0, and N.O. to port 1, and so on.
* Address select ports should be set for pull-up, connect to ground for "1".
* Address bus is just a normal TTL, 1 = 1.
### Todo
* individual folders for different CPLD/FPGAs (Verilog + Constraints and Schematics). This will be limited to what I have available.