https://github.com/ellisgl/driver-yl-3

Verilog code to run the YL-3 8 digit 7 segment display.
https://github.com/ellisgl/driver-yl-3

seven-segment verilog

Last synced: about 2 months ago
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Verilog code to run the YL-3 8 digit 7 segment display.

• Host: GitHub
• URL: https://github.com/ellisgl/driver-yl-3
• Owner: ellisgl
• License: bsd-3-clause
• Created: 2015-12-31T22:17:12.000Z (about 9 years ago)
• Default Branch: release
• Last Pushed: 2020-06-28T03:21:32.000Z (over 4 years ago)
• Last Synced: 2023-03-18T05:10:28.824Z (almost 2 years ago)
• Topics: seven-segment, verilog
• Language: Verilog
• Size: 27.4 MB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0

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