https://github.com/ellisgl/sap-1-v2-mojo

SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.
https://github.com/ellisgl/sap-1-v2-mojo

cpu fpga mojo-fpga-board verilog

Last synced: about 2 months ago
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SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.

• Host: GitHub
• URL: https://github.com/ellisgl/sap-1-v2-mojo
• Owner: ellisgl
• Created: 2016-06-15T14:47:19.000Z (over 8 years ago)
• Default Branch: release
• Last Pushed: 2020-06-28T04:30:09.000Z (over 4 years ago)
• Last Synced: 2023-03-18T05:10:29.179Z (almost 2 years ago)
• Topics: cpu, fpga, mojo-fpga-board, verilog
• Language: Verilog
• Homepage:
• Size: 27.3 KB
• Stars: 11
• Watchers: 4
• Forks: 5
• Open Issues: 0

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