https://github.com/elvircrn/psds-labs

VHDL Samples
https://github.com/elvircrn/psds-labs

logic-design vhdl

Last synced: 6 months ago
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VHDL Samples

• Host: GitHub
• URL: https://github.com/elvircrn/psds-labs
• Owner: elvircrn
• Created: 2016-11-03T09:14:39.000Z (over 9 years ago)
• Default Branch: master
• Last Pushed: 2018-04-29T23:43:14.000Z (about 8 years ago)
• Last Synced: 2025-07-27T02:34:09.726Z (12 months ago)
• Topics: logic-design, vhdl
• Language: VHDL
• Homepage:
• Size: 6.84 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# Shifting

``` 

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

shifted <= to_stdlogicvector (to_bitvector (a) sll 	(signed(ctrl)));

shifted <= std_logic_vector(shift_left(signed(a), to_integer(unsigned(ctrl))));

```