https://github.com/emrys-hong/sutd-minihardware-project
1D minihard-ware project FPGA part, using lucid to programe FPGA to test whether "full adder" is functional.
https://github.com/emrys-hong/sutd-minihardware-project
Last synced: 3 months ago
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1D minihard-ware project FPGA part, using lucid to programe FPGA to test whether "full adder" is functional.
- Host: GitHub
- URL: https://github.com/emrys-hong/sutd-minihardware-project
- Owner: Emrys-Hong
- Created: 2018-09-29T10:04:23.000Z (over 6 years ago)
- Default Branch: master
- Last Pushed: 2018-10-10T09:38:53.000Z (over 6 years ago)
- Last Synced: 2025-01-15T08:19:19.425Z (4 months ago)
- Language: Verilog
- Size: 721 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Minihardware-project-SUTD
1D minihard-ware project FPGA part, using lucid to programe FPGA to test whether "full adder" is functional.
will show "good", on io_sel board if all the cases passes, and will show "ERR " if one case fails.
you can view a more detailed version on [my logbook](https://www.evernote.com/l/AoLmKouIknROm4UlzPOVdCkO6-1b6Nncipw)