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https://github.com/emrys-hong/sutd-minihardware-project

1D minihard-ware project FPGA part, using lucid to programe FPGA to test whether "full adder" is functional.
https://github.com/emrys-hong/sutd-minihardware-project

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1D minihard-ware project FPGA part, using lucid to programe FPGA to test whether "full adder" is functional.

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# Minihardware-project-SUTD
1D minihard-ware project FPGA part, using lucid to programe FPGA to test whether "full adder" is functional.

will show "good", on io_sel board if all the cases passes, and will show "ERR " if one case fails.

you can view a more detailed version on [my logbook](https://www.evernote.com/l/AoLmKouIknROm4UlzPOVdCkO6-1b6Nncipw)