https://github.com/enderturtleorz/5-stage-pipelined-cpu-mips32

Project 3 of CSC3050, 2023 Spring, CUHK(SZ)
https://github.com/enderturtleorz/5-stage-pipelined-cpu-mips32

Last synced: 13 days ago
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Project 3 of CSC3050, 2023 Spring, CUHK(SZ)

• Host: GitHub
• URL: https://github.com/enderturtleorz/5-stage-pipelined-cpu-mips32
• Owner: EnderturtleOrz
• Created: 2024-03-27T08:08:43.000Z (11 months ago)
• Default Branch: master
• Last Pushed: 2024-03-27T08:23:51.000Z (11 months ago)
• Last Synced: 2024-11-24T22:16:41.618Z (2 months ago)
• Language: Verilog
• Size: 307 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Project Description

This is my implementation for the course project 3 of CSC3050, 2023 Spring, CUHK(SZ). In this project, we are required to write a simple ALU and a 5-stage Pipelined CPU.

# Set Up Instruction

## Prerequisites

- iverilog

- Make >= 4.2.1

## Compile the project

```shell

$ cd /path/to/the/project/src/alu

$ make compile

$ cd /path/to/the/project/src/cpu

$ make compile

```

# Report

A more detailed report can be found in [here](https://github.com/EnderturtleOrz/5-Stage-Pipelined-CPU-MIPS32/blob/master/report/report.pdf)