https://github.com/enjoy-digital/litex_verilog_axi_test

Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.
https://github.com/enjoy-digital/litex_verilog_axi_test

Last synced: 3 months ago
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Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.

• Host: GitHub
• URL: https://github.com/enjoy-digital/litex_verilog_axi_test
• Owner: enjoy-digital
• Created: 2022-06-06T07:33:59.000Z (over 2 years ago)
• Default Branch: master
• Last Pushed: 2022-12-19T20:35:34.000Z (about 2 years ago)
• Last Synced: 2024-08-03T01:38:27.044Z (6 months ago)
• Language: Python
• Size: 164 KB
• Stars: 14
• Watchers: 5
• Forks: 5
• Open Issues: 3
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
[> Intro

--------

This repository is an experiment to wrap Alex Forenchich's Verilog-AXI core with LiteX to easily compose AXI systems with it.

[> AXI-Lite Status

---------------------

| Module            | Status                     |

|-------------------|----------------------------|

| axil_adapter      | Done, passing simple tests |

| axil_cdc          | Done, passing simple tests |

| axil_crossbar     | Done, passing simple tests |

| axil_dp_ram       | Done, passing simple tests |

| axil_interconnect | Done, passing simple tests |

| axil_ram          | Done, passing simple tests |

| axil_register     | Done, passing simple tests |

[> AXI <-> AXI-Lite Status

--------------------------

| Module            | Status                                           |

|-------------------|--------------------------------------------------|

| axi_axil_adapter  | Done, passing simple tests                       |

[> AXI Status

----------------

| Module            | Status                                           |

|-------------------|--------------------------------------------------|

| axi_adapter       | Done, Verilator compil issue                     |

| axi_cdma          | Wrapped, need testing                            |

| axi_crossbar      | Done, passing simple tests                       |

| axi_dma           | Wrapped, need testing                            |

| axi_dp_ram        | Done, passing simple tests                       |

| axi_fifo          | Done, passing simple tests                       |

| axi_interconnect  | Done, passing simple tests                       |

| axi_ram           | Done, passing simple tests                       |

| axi _register     | Done, passing simple tests                       |