Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
https://github.com/eomielan/16-bit-risc-machine
16-bit CPU architecture implementation and verification using SystemVerilog
https://github.com/eomielan/16-bit-risc-machine
cpu-architecture systemverilog verilog
Last synced: about 10 hours ago
JSON representation
16-bit CPU architecture implementation and verification using SystemVerilog
- Host: GitHub
- URL: https://github.com/eomielan/16-bit-risc-machine
- Owner: eomielan
- Created: 2023-08-29T03:41:20.000Z (about 1 year ago)
- Default Branch: main
- Last Pushed: 2024-08-28T23:51:10.000Z (2 months ago)
- Last Synced: 2024-08-30T00:06:57.111Z (2 months ago)
- Topics: cpu-architecture, systemverilog, verilog
- Homepage:
- Size: 179 KB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# 16-bit RISC Machine
The 16-bit RISC Machine project focused on designing and implementing a Central Processing Unit (CPU) architecture using SystemVerilog. This included a Finite State Machine (FSM) controller, instruction decoder, Arithmetic Logic Unit (ALU), memory unit, and program counter.
To validate the correctness of each individual component and the CPU as a complete system, my partner and I wrote a set of testbenches using SystemVerilog and executed them in ModelSim. This allowed us to identify failures in specific modules and test the integration of the CPU components.
The code is available uppon request. Please send an email to [[email protected]](mailto:[email protected]) or [[email protected]](mailto:[email protected]).
## Diagram
## Supported Instructions
