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https://github.com/ernanej/cachesim-mapping-ca
Simulation of a computational system with a single cache between processor and main memory to test various configurations of cache designs and obtain the existing hit and miss rates.
https://github.com/ernanej/cachesim-mapping-ca
cache cachesim dca0104 pycachesim
Last synced: 14 days ago
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Simulation of a computational system with a single cache between processor and main memory to test various configurations of cache designs and obtain the existing hit and miss rates.
- Host: GitHub
- URL: https://github.com/ernanej/cachesim-mapping-ca
- Owner: ErnaneJ
- Created: 2023-06-02T03:12:35.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2023-06-05T03:14:22.000Z (over 1 year ago)
- Last Synced: 2024-05-01T14:30:06.686Z (6 months ago)
- Topics: cache, cachesim, dca0104, pycachesim
- Language: Python
- Homepage:
- Size: 861 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0