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https://github.com/et1975/stm32l4x5
(WIP) Peripheral access API for STM32L4x5 microcontrollers
https://github.com/et1975/stm32l4x5
arm cortex-m microcontroller no-std peripherals rust stm32 svd2rust
Last synced: 8 days ago
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(WIP) Peripheral access API for STM32L4x5 microcontrollers
- Host: GitHub
- URL: https://github.com/et1975/stm32l4x5
- Owner: et1975
- License: apache-2.0
- Created: 2017-12-19T22:18:53.000Z (about 7 years ago)
- Default Branch: master
- Last Pushed: 2018-03-22T20:32:10.000Z (almost 7 years ago)
- Last Synced: 2024-11-05T20:06:55.648Z (about 2 months ago)
- Topics: arm, cortex-m, microcontroller, no-std, peripherals, rust, stm32, svd2rust
- Language: Rust
- Homepage:
- Size: 686 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE-APACHE
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README
# `stm32l4x5`
> Peripheral access API for STM32L4x5 microcontrollers
Generated from http://www.st.com/resource/en/svd/stm32l4_svd.zip with svd2rust v0.12.0
# Issues
WARNING ccmr1_input overlaps with another register at offset 24. Ignoring.
WARNING ccmr2_input overlaps with another register at offset 28. Ignoring.
WARNING ccmr1_input overlaps with another register at offset 24. Ignoring.
WARNING ccmr1_input overlaps with another register at offset 24. Ignoring.
WARNING ccmr1_input overlaps with another register at offset 24. Ignoring.
WARNING ccmr2_input overlaps with another register at offset 28. Ignoring.
WARNING ccmr1_input overlaps with another register at offset 24. Ignoring.
WARNING ccmr2_input overlaps with another register at offset 28. Ignoring.# License
Licensed under either of
- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
http://www.apache.org/licenses/LICENSE-2.0)- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
at your option.
## Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
dual licensed as above, without any additional terms or conditions.