https://github.com/eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
https://github.com/eugene-tarassov/vivado-risc-v

arty-a7 boom fpga genesys2 kc705 linux nexys-video risc-v riscv rocketchip vc707 vivado xilinx

Last synced: 3 months ago
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Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

• Host: GitHub
• URL: https://github.com/eugene-tarassov/vivado-risc-v
• Owner: eugene-tarassov
• Created: 2020-02-15T01:12:54.000Z (almost 5 years ago)
• Default Branch: master
• Last Pushed: 2024-11-01T06:08:06.000Z (3 months ago)
• Last Synced: 2024-11-01T07:17:46.765Z (3 months ago)
• Topics: arty-a7, boom, fpga, genesys2, kc705, linux, nexys-video, risc-v, riscv, rocketchip, vc707, vivado, xilinx
• Language: Tcl
• Homepage:
• Size: 36.1 MB
• Stars: 837
• Watchers: 36
• Forks: 190
• Open Issues: 48
• Metadata Files:
  • Readme: README.md

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